`timescale 1ns/100ps

module lvds #(
  parameter   FPGA_TECHNOLOGY = 1,
  parameter   IODELAY_ENABLE = 0,
  parameter   IODELAY_ENABLE_RX = 0,
  parameter   IO_DELAY_GROUP = "line_delay",
  parameter   IODELAY_CTRL = 0,
  parameter   CLK_DESKEW = 0,
  parameter   USE_MCLK = 1,
  parameter   USE_CLK_DELAY =0,
  parameter   DELAY_REFCLK_FREQUENCY = 100,
  parameter   USE_TX_CLKSEL =0
) (
  // physical interface (receive)
  input               rx_clk_in_p,
  input               rx_clk_in_n,
  input               rx_frame_in_p,
  input               rx_frame_in_n,
  input   [ 5:0]      rx_data_in_p,
  input   [ 5:0]      rx_data_in_n,

  // physical interface (transmit)

  output              tx_clk_out_p,
  output              tx_clk_out_n,
  output              tx_frame_out_p,
  output              tx_frame_out_n,
  output  [ 5:0]      tx_data_out_p,
  output  [ 5:0]      tx_data_out_n,



  // clock (common to both receive and transmit)
  input               rst_n,
  input               skew_clk,//used to skew or replace m_clk
  output              m_clk,  //pin clock

  // receive data path interface
  output              adc_valid,
  output  [47:0]      adc_data,
  output              adc_status,
  input               adc_r1_mode,

  // transmit data path interface
  input               dac_valid,
  input   [47:0]      dac_data,
  input               dac_clk_inv,
  input               dac_r1_mode,


  // delay interface
  input               up_clk, //used to load delay value
  input   [ 6:0]      up_adc_dld,
  input   [34:0]      up_adc_dwdata,
  output  [34:0]      up_adc_drdata,
  input   [ 9:0]      up_dac_dld,
  input   [49:0]      up_dac_dwdata,
  output  [49:0]      up_dac_drdata,
  input               delay_clk,//used to product delay ,always 200Mhz
  input               delay_rstn,
  output              delay_locked
);

  // internal registers
  reg                 rx_r1_mode = 'd0;
  reg                 rx_locked_m1 = 'd0;
  reg                 rx_locked = 'd0;
  reg     [ 1:0]      rx_frame = 'd0;
  reg     [ 5:0]      rx_data_1 = 'd0;
  reg     [ 5:0]      rx_data_0 = 'd0;
  reg                 adc_valid_p = 'd0;
  reg     [47:0]      adc_data_p = 'd0;
  reg                 adc_status_p = 'd0;
  reg                 adc_valid_int = 'd0;
  reg     [47:0]      adc_data_int = 'd0;
  reg                 adc_status_int = 'd0;
  reg     [ 1:0]      tx_data_sel = 'd0;
  reg     [47:0]      tx_data = 'd0;
  reg     [ 1:0]      tx_clk_p = 'd0;
  reg                 tx_frame_p = 'd0;
  reg     [ 5:0]      tx_data_0_p = 'd0;
  reg     [ 5:0]      tx_data_1_p = 'd0;
  reg     [ 1:0]      tx_clk = 'd0;
  reg                 tx_frame = 'd0;
  reg     [ 5:0]      tx_data_0 = 'd0;
  reg     [ 5:0]      tx_data_1 = 'd0;

  // internal signals

  wire    [ 5:0]      rx_data_1_s;
  wire    [ 5:0]      rx_data_0_s;
  wire    [ 1:0]      rx_frame_s;
  wire                locked_s;

  // drp interface signals

//  assign up_drp_rdata = 32'd0;
//  assign up_drp_ready = 1'd0;
//  assign up_drp_locked = 1'd1;

  // r1mode

  generate if (CLK_DESKEW) begin

    reg adc_r1_mode_n = 'd0;

    always @(negedge skew_clk) begin
      adc_r1_mode_n <= adc_r1_mode;
    end

    always @(posedge m_clk) begin
      rx_r1_mode <= adc_r1_mode_n;
    end

  end else begin /* CLK_DESKEW == 0 */

    always @(posedge m_clk) begin
      rx_r1_mode <= adc_r1_mode;
    end

  end
  endgenerate

  // adc-status
  assign delay_locked = locked_s;

  always @(posedge m_clk) begin
    rx_locked_m1 <= locked_s;
    rx_locked <= rx_locked_m1;
  end

  // intel-equivalence
  always @(posedge m_clk) begin
    rx_frame <= rx_frame_s;
    rx_data_1 <= rx_data_1_s;
    rx_data_0 <= rx_data_0_s;
  end

  // frame check

  // delineation
  reg             rx_error_r1 = 'd0;
  reg             rx_error_r2 = 'd0;

  always @(posedge m_clk) begin
    rx_error_r1 <= ~((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011));
    rx_error_r2 <= ~((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) ||
                     (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011));
  end
  
 

  always @(posedge m_clk) begin
      case ({rx_r1_mode, rx_frame_s, rx_frame})
        5'b01111: begin
          adc_valid_p <= 1'b0;
          adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
          adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
        end
        5'b00000: begin
          adc_valid_p <= 1'b1;
          adc_data_p[47:36] <= {rx_data_1, rx_data_1_s};
          adc_data_p[35:24] <= {rx_data_0, rx_data_0_s};
        end
        5'b10011: begin
          adc_valid_p <= 1'b1;
          adc_data_p[47:24] <= 24'd0;
          adc_data_p[23:12] <= {rx_data_1, rx_data_1_s};
          adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s};
        end
        default: begin
          adc_valid_p <= 1'b0;
        end
      endcase
  end

  // adc-status

  always @(posedge m_clk) begin
    if (adc_r1_mode == 1'b1) begin
      adc_status_p <= ~rx_error_r1 & rx_locked;
    end else begin
      adc_status_p <= ~rx_error_r2 & rx_locked;
    end
  end

  // transfer to common clock

  generate if (CLK_DESKEW) begin

    reg         adc_valid_n = 'd0;
    reg [47:0]  adc_data_n = 'd0;
    reg         adc_status_n = 'd0;

    always @(negedge skew_clk) begin
      adc_valid_n <= adc_valid_p;
      adc_data_n <= adc_data_p;
      adc_status_n <= adc_status_p;
    end

    always @(posedge m_clk) begin
      adc_valid_int <= adc_valid_n;
      adc_data_int <= adc_data_n;
      adc_status_int <= adc_status_n;
    end

    assign adc_valid = adc_valid_int;
    assign adc_data = adc_data_int;
    assign adc_status = adc_status_int;

  end else begin /* CLK_DESKEW == 0 */

    always @(posedge m_clk) begin
      adc_valid_int <= adc_valid_p;
      adc_data_int <= adc_data_p;
      adc_status_int <= adc_status_p;
    end

    assign adc_valid = adc_valid_int;
    assign adc_data = adc_data_int;
    assign adc_status = adc_status_int;

  end
  endgenerate

  // dac-tx interface

  always @(posedge m_clk) begin
    if (dac_valid == 1'b1) begin
      tx_data_sel <= 2'b00;
    end else begin
      tx_data_sel <= tx_data_sel + 1'b1;
    end
    if (dac_valid == 1'b1) begin
      tx_data <= dac_data;
    end
  end

  always @(posedge m_clk) begin
    tx_clk_p <= {~dac_clk_inv, dac_clk_inv};
  end

  always @(posedge m_clk) begin
    case ({dac_r1_mode, tx_data_sel})
      3'b000: begin
        tx_frame_p <= 1'b1;
        tx_data_0_p <= tx_data[11:6];
        tx_data_1_p <= tx_data[23:18];
      end
      3'b001: begin
        tx_frame_p <= 1'b1;
        tx_data_0_p <= tx_data[5:0];
        tx_data_1_p <= tx_data[17:12];
      end
      3'b010: begin
        tx_frame_p <= 1'b0;
        tx_data_0_p <= tx_data[35:30];
        tx_data_1_p <= tx_data[47:42];
      end
      3'b011: begin
        tx_frame_p <= 1'b0;
        tx_data_0_p <= tx_data[29:24];
        tx_data_1_p <= tx_data[41:36];
      end
      3'b100: begin
        tx_frame_p <= 1'b1;
        tx_data_0_p <= tx_data[11:6];
        tx_data_1_p <= tx_data[23:18];
      end
      3'b101: begin
        tx_frame_p <= 1'b0;
        tx_data_0_p <= tx_data[5:0];
        tx_data_1_p <= tx_data[17:12];
      end
      default: begin
        tx_frame_p <= 1'b0;
        tx_data_0_p <= 6'd0;
        tx_data_1_p <= 6'd0;
      end
    endcase
  end

  // transfer to local clock
  generate if (CLK_DESKEW) begin

    reg [ 1:0]  tx_clk_n = 'd0;
    reg         tx_frame_n = 'd0;
    reg [ 5:0]  tx_data_0_n = 'd0;
    reg [ 5:0]  tx_data_1_n = 'd0;

    always @(negedge skew_clk) begin
      tx_clk_n <= tx_clk_p;
      tx_frame_n <= tx_frame_p;
      tx_data_0_n <= tx_data_0_p;
      tx_data_1_n <= tx_data_1_p;
    end

    always @(posedge m_clk) begin
      tx_clk <= tx_clk_n;
      tx_frame <= tx_frame_n;
      tx_data_0 <= tx_data_0_n;
      tx_data_1 <= tx_data_1_n;
    end

  end else begin /* CLK_DESKEW == 0 */

    always @(posedge m_clk) begin
      tx_clk <= tx_clk_p;
      tx_frame <= tx_frame_p;
      tx_data_0 <= tx_data_0_p;
      tx_data_1 <= tx_data_1_p;
    end

  end
  endgenerate

  // receive data interface, ibuf -> idelay -> iddr

  genvar i;
  generate
  for (i = 0; i < 6; i = i + 1) begin: g_rx_data
  ad_data_in #(
    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
    .IODELAY_ENABLE (IODELAY_ENABLE_RX),
    .IODELAY_CTRL (IODELAY_CTRL),
    .IODELAY_GROUP (IO_DELAY_GROUP),
    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
  ) i_rx_data (
    .m_clk (m_clk),
    .rx_data_in_p (rx_data_in_p[i]),
    .rx_data_in_n (rx_data_in_n[i]),
    .rx_data_p (rx_data_1_s[i]),
    .rx_data_n (rx_data_0_s[i]),
    .up_clk (up_clk),
    .up_dld (up_adc_dld[i]),
    .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]),
    .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]),
    .delay_clk (delay_clk),
    .delay_rst (!delay_rstn),
    .delay_locked ());
  end
  endgenerate

  // receive frame interface, ibuf -> idelay -> iddr
  ad_data_in #(
    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
    .IODELAY_ENABLE (IODELAY_ENABLE_RX),
    .IODELAY_CTRL (IODELAY_CTRL),
    .IODELAY_GROUP (IO_DELAY_GROUP),
    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
  ) i_rx_frame (
    .m_clk (m_clk),
    .rx_data_in_p (rx_frame_in_p),
    .rx_data_in_n (rx_frame_in_n),
    .rx_data_p (rx_frame_s[1]),
    .rx_data_n (rx_frame_s[0]),
    .up_clk (up_clk),
    .up_dld (up_adc_dld[6]),
    .up_dwdata (up_adc_dwdata[34:30]),
    .up_drdata (up_adc_drdata[34:30]),
    .delay_clk (delay_clk),
    .delay_rst (!delay_rstn),
    .delay_locked (locked_s));
  // transmit data interface, oddr -> obuf

  generate
  for (i = 0; i < 6; i = i + 1) begin: g_tx_data
  ad_data_out #(
    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
    .IODELAY_ENABLE (IODELAY_ENABLE),
    .IODELAY_CTRL (IODELAY_CTRL),
    .IODELAY_GROUP (IO_DELAY_GROUP),
    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
  ) i_tx_data (
    .tx_clk (m_clk),
    .tx_data_p (tx_data_1[i]),
    .tx_data_n (tx_data_0[i]),
    .tx_data_out_p (tx_data_out_p[i]),
    .tx_data_out_n (tx_data_out_n[i]),
    .up_clk (up_clk),
    .up_dld (up_dac_dld[i]),
    .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]),
    .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]),
    .delay_clk (delay_clk),
    .delay_rst (!delay_rstn),
    .delay_locked ());
  end
  endgenerate

  // transmit frame interface, oddr -> obuf
  ad_data_out #(
    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
    .IODELAY_ENABLE (IODELAY_ENABLE),
    .IODELAY_CTRL (IODELAY_CTRL),
    .IODELAY_GROUP (IO_DELAY_GROUP),
    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
  ) i_tx_frame (
    .tx_clk (m_clk),
    .tx_data_p (tx_frame),
    .tx_data_n (tx_frame),
    .tx_data_out_p (tx_frame_out_p),
    .tx_data_out_n (tx_frame_out_n),
    .up_clk (up_clk),
    .up_dld (up_dac_dld[6]),
    .up_dwdata (up_dac_dwdata[34:30]),
    .up_drdata (up_dac_drdata[34:30]),
    .delay_clk (delay_clk),
    .delay_rst (!delay_rstn),
    .delay_locked ());

  // transmit clock interface, oddr -> obuf
  ad_data_out #(
    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
    .IODELAY_ENABLE (IODELAY_ENABLE),
    .IODELAY_CTRL (IODELAY_CTRL),
    .IODELAY_GROUP (IO_DELAY_GROUP),
    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
  ) i_tx_clk (
    .tx_clk (m_clk),
    .tx_data_p (tx_clk[1]),
    .tx_data_n (tx_clk[0]),
    .tx_data_out_p (tx_clk_out_p),
    .tx_data_out_n (tx_clk_out_n),
    .up_clk (up_clk),
    .up_dld (up_dac_dld[7]),
    .up_dwdata (up_dac_dwdata[39:35]),
    .up_drdata (up_dac_drdata[39:35]),
    .delay_clk (delay_clk),
    .delay_rst (!delay_rstn),
    .delay_locked ());

  
  //--------------- CLK IN ------------
  wire l_clk_delay;
  // device clock interface (receive clock)
  generate if (USE_MCLK == 1) begin
  ad_data_clk i_clk (
    .rst (!rst_n),
    .locked (),
    .clk_in_p (rx_clk_in_p),
    .clk_in_n (rx_clk_in_n),
    .clk (l_clk_delay));
  end else begin
    assign l_clk_delay = skew_clk;
  end
  endgenerate
  
  
  generate if (USE_CLK_DELAY == 1 || IODELAY_ENABLE ==1 || IODELAY_ENABLE_RX==1) begin
    (* IODELAY_GROUP = IO_DELAY_GROUP *)
    IDELAYCTRL #(
      .SIM_DEVICE ("7SERIES")
    ) i_delay_ctrl (
      .RST (!delay_rstn),
      .REFCLK (delay_clk),
      .RDY ());
  end
  endgenerate
  
  generate if (USE_CLK_DELAY == 1) begin
  (* IODELAY_GROUP = IO_DELAY_GROUP *)
  IDELAYE2 #(
     .CINVCTRL_SEL("FALSE"),                      // Enable dynamic clock inversion (FALSE, TRUE)
     .DELAY_SRC("IDATAIN"),                       // Delay input (IDATAIN, DATAIN)
     .HIGH_PERFORMANCE_MODE("FALSE"),         // Reduced jitter ("TRUE"), Reduced power ("FALSE")
     .IDELAY_TYPE("FIXED"),                       // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
     .IDELAY_VALUE(15),                                // Input delay tap setting (0-31)
     .PIPE_SEL("FALSE"),                              // Select pipelined mode, FALSE, TRUE
     .REFCLK_FREQUENCY(DELAY_REFCLK_FREQUENCY),                    // IDELAYCTRL clock input frequency in MHz (190.0-210.0, 290.0-310.0).
     .SIGNAL_PATTERN("DATA")                      // DATA, CLOCK input signal
  )
  IDELAYE2_inst (
     .CNTVALUEOUT(),     // 5-bit output: Counter value output
     .DATAOUT(m_clk),         // 1-bit output: Delayed data output
     .C(delay_clk),                                     // 1-bit input: Clock input
     .CE(1'b0),                                   // 1-bit input: Active high enable increment/decrement input
     .CINVCTRL(1'b0),                           // 1-bit input: Dynamic clock inversion input
     .CNTVALUEIN(5'd5),                           // 5-bit input: Counter value input
     .DATAIN(1'b0),                               // 1-bit input: Internal delay data input
     .IDATAIN(l_clk_delay),             // 1-bit input: Data input from the I/O
     .INC(1'b0),                         // 1-bit input: Increment / Decrement tap delay input
     .LD(1'b0),                                           // 1-bit input: Load IDELAY_VALUE input
     .LDPIPEEN(1'b0),                           // 1-bit input: Enable PIPELINE register to load data input
     .REGRST(!delay_rstn)                            // 1-bit input: Active-high reset tap-delay input
  );
  
  end else begin
  assign m_clk =  l_clk_delay;
  end
  endgenerate
  //--------------- CLK IN ------------
endmodule
